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Wireless Components
2 Band TV Tuner Mixer-Oscillator-PLL with balanced IF-Amplifier TUA6020 Version 1.1
Specification March 2000
preliminary
Revision History: Current Version: 03.00 Previous Version:Target Data Sheet Page (in previous Version) 5-8, 5-9 all Page (in current Version) 5-8, 5-9 all Subjects (major changes since last revision)
oscillator phase noise data status: target to preliminary
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Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG i. Gr. 22.03.00. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
TUA6020
preliminary
Product Info
Product Info
General Description The TUA6020 is a 5 V mixer/oscillator Package and sythesizer for analog and digital TV and VCR tuners. General Suitable for analog and digital terrestrial TV tuner Full ESD protection
Features
4 pin oscillator for HIGH band IF-Amplifier balanced SAW preamplifier Low output impedance
PLL PLL with short lock-in time High voltage VCO tuning output
Ordering Information
Type TUA6020 Ordering Code Q67037-A1127 (tape and reel) Package P-TSSOP-28-1
Wireless Components
Application
The IC is suitable for PAL tuner in TV- and VCR-sets or set-top receivers for analog TV and Digital Video Broadcasting.
Product Info

Mixer/Oscillator High impedance mixer input for LOW/MID band Low impedance mixer input for HIGH band 4 pin oscillator for LOW/MID band Fast I2C bus 3 NPN bandswitch buffers Internal LOW-MID/HIGH switch Lock-in flag Power-down reset Programmable reference divider ratios: 24, 64, 80, 128 Programmable charge pump current
Specification, March 2000
1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 4 4.1 5 5.1 5.1.1 5.1.2 5.1.3
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-9 IC frequency range selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Gain (GV) test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . . . . 5-13 Gain (GV) test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Matching circuit for optimum noise figure in LOW/MID band . . . . . . 5-14 Noise Figure Test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . 5-14 Noise Figure Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . 5-15 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-15
Wireless Components
1-1
Specification, March 2000
TUA6020
target
Table of Contents
5.4.7 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-16 5.4.8 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.5 5.5.1 5.5.2 5.5.3 5.5.4 Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-17 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-17 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-18 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-18
Wireless Components
1-2
Specification, March 2000
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Wireless Components
2-1
Specification, March 2000
TUA6020
preliminary
Product Description
2.1 General Description
The TUA6020 device combines a digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV and VCR tuners. The PLL block with four selectable chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 1024 MHz in increments of 31.25, 50, 62.5 or 166.7 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has three output ports. A flag is set when the loop is locked it can be read by the processor via the I2C bus. The mixer-oscillator block includes two balanced mixers (one mixer with highimpedance input and one mixer with a balanced low-impedance input), two frequency and amplitude-stable balanced oscillators for LOW/MID and HIGH, an IF amplifier, a low-noise reference voltage source, and a band switch.
2.2 Features
General Suitable for analog and digital terrestrial TV tuner Full ESD protection
Wireless Components

Mixer/Oscillator High impedance mixer input for LOW/MID band Low impedance mixer input for HIGH band 4 pin oscillator for LOW/MID band 4 pin oscillator for HIGH band
IF-Amplifier balanced SAW preamplifier Low output impedance
PLL PLL with short lock-in time High voltage VCO tuning output Fast I2C bus 3 NPN bandswitch buffers Internal LOW-MID/HIGH switch Lock-in flag Power-down reset
2-2
Specification, March 2000
TUA6020
preliminary
Product Description
Programmable reference divider ratios: 24, 64, 80, 128 Programmable charge pump current
2.3 Application
2.4 Package Outlines
Wireless Components

The IC is suitable for PAL tuners in TV- and VCR-sets or set-top receivers for analog TV and Digital Video Broadcasting.
P-TSSOP-28-1
2-3
Specification, March 2000
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Wireless Components
3-1
Specification, March 2000
TUA6020
preliminary
Confidential
Functional Description
3.1 Pin Configuration
HIGHIN HIGHIN LOW/MIDIN VCC MIXOUT MIXOUT PLLGND SDA SCL AS XTAL PHIGH PLOW PMID
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
OSCHIGHIN OSCHIGHOUT OSCHIGHOUT OSCHIGHIN OSCLOW/MIDIN OSCLOW/MIDOUT OSCLOW/MIDOUT OSCLOW/MIDIN RFGND VCC *) IFOUT IFOUT VT CP
TUA6020
22 21 20 19 18 17 16 15
*) for future purposes
Pin_config
Figure 3-1
Pin Configuration
Wireless Components
3-2
Specification, March 2000
TUA6020
preliminary
Confidential
Functional Description
3.2 Internal Pin Configuration
Table 3-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 1 HIGHIN 0.0 V HIGH 0.9 V
2
HIGHIN
1
2
0.0 V
0.9 V
3
LOW/MIDIN
1.8 V
0.0 V
3
4 5
VCC MIXOUT
supply voltage
5.0 V 3.8 V
IF Amp.
5.0 V 3.8 V
6
MIXOUT
5
6
3.8 V
3.8 V
Oscillator
7
PLLGND
digital ground
0.0 V
0.0 V
Wireless Components
3-3
Specification, March 2000
TUA6020
preliminary
Confidential
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 8 SDA n.a. HIGH n.a.
8
9
SCL
n.a.
n.a.
9
10
AS
VAS
VAS
10
11
XTAL
3.0 V
3.0 V
11
Wireless Components
3-4
Specification, March 2000
TUA6020
preliminary
Confidential
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 12 PHIGH
12 13 14
HIGH VCE
5V
13
PLOW
5 V or V CE
5V
14
PMID
5 V or V CE
5V
15
CP
1.9 V
1.9 V
15
16
VT
16
VT
VT
17
IFOUT
2.3 V
2.3 V
17
18
18
IFOUT
2.3 V
2.3 V
19 20
VCC RFGND
supply voltage analog ground
5.0 V 0.0 V
5.0 V 0.0 V
Wireless Components
3-5
Specification, March 2000
TUA6020
preliminary
Confidential
Functional Description
Table 3-1 Pin Definition and Function (continued) Pin No. Symbol Equivalent I/O-Schematic Average DC voltage LOW/MID 21 OSCLOW/ MIDIN 1.6 V HIGH 0.0 V
22
OSCLOW/ MIDOUT
22
23
2.3 V
0.0 V
21
24
23
OSCLOW/ MIDOUT
2.3 V
0.0 V
24
OSCLOW/ MIDIN OSCHIGHIN OSCHIGHOUT OSCHIGHOUT OSCHIGHIN
25 28 26 27
1.6 V
0.0 V
25 26 27 28
0.0 V 0.0 V 0.0 V 0.0 V
1.6 V 2.8 V 2.8 V 1.6 V
Wireless Components
3-6
Specification, March 2000
TUA6020
preliminary
Confidential
Functional Description
3.3 Block Diagram
OSCLOW/MIDOUT
OSCLOW/MIDOUT
OSCLOW/MIDIN
OSCHIGHOUT
OSCHIGHIN
OSCHIGHIN
OSCLOW/MIDIN
OSCHIGHOUT
RFGND
IFOUT
VCC
IFOUT
28
27
26
25
24
23
22
21
20
19
18
17
16
VT
Charge Pump
fdiv
15
Oscillator HIGH
HIGH LOW or MID
Oscillator LOW/MID
SAW Driver
Phase/ Frequency Comparator
CP, OS fref
Prog. Divider
Reference Divider Mixer HIGH
HIGH LOW or MID
Mixer LOW/MID Lock Detector Crystal Oscillator
RF Input HIGH
HIGH LOW or MID VCC
RF Input LOW/MID
FL
I2C Bus
PORTS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LOW/MIDIN
PLLGND
HIGHIN
HIGHIN
MIXOUT
MIXOUT
PHIGH
XTAL
PLOW
PMID
Block_diag
VCC
SDA
Figure 3-2
Block Diagram
Wireless Components
3-7
SCL
AS
Specification, March 2000
CP
TUA6020
preliminary
Confidential
Functional Description
3.4 Circuit Description
3.4.1
Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for LOW/MID and HIGH, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switching in the tuner front-end is done by using two or three port outputs. In the selected band the signal passes a tuner input stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has in case of LOW / MID a high-impedance input and in case of HIGH a low-impedance input. The input signal is mixed there with the signal from the activated on chip oscillator to the IF frequency which is filtered out at the balanced high-impedance output pair by means of a parallel tuned circuit. The following SAW preamplifier has a low output impedance to drive the SAW filter directly.
3.4.2
PLL block
The oscillator signal is internally DC-coupled as a differential signal to the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency fref = 31.25, 50, 62.5 or 166.7 kHz.This frequency is derived from a unbalanced, low-impedance 4 MHz crystal oscillator (pin XTAL) divided by R = 128, 80, 64 or 24. The phase detector has two outputs that drive two current sources of opposite palarity as charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the positive current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state if the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments. If the VCO is not oscillating the PLL locks to a tuning voltage of 33V (VTH). By means of control bit CP the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example.
Wireless Components
3-8
Specification, March 2000
TUA6020
preliminary
Confidential
Functional Description
The software-switched ports PLOW, PMID and PHIGH are general-purpose open-collector outputs. The test bit T1 = 1, switches the test signals fref (i.e.fXTAL / 64) and fdiv (divided input signal) to PLOW and PMID respectively. The lock detector resets the lock flag FL if the width of the charge pump current pulses is wider than the period of the crystal oscillator (i.e. 250 ns). Hence, if FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by f == I P (KVCO / fXTAL) =(C1+C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fXTAL the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see Figure 4-1 Evaluation Board on page 2). As the charge pump pulses at i.e. 62.5 kHz (= fref), it takes a maximum of 16=s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144=s for FL to be set after the loop regains lock.
3.4.3
I2C-Bus Interface
Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table "Bit Allocation" (see Table 5-4 Bit Allocation Read / Write on page 10) should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte.
Wireless Components
3-9
Specification, March 2000
TUA6020
preliminary
Confidential
Functional Description
If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists the lock flag and the power-on flag. Four different chip addresses can be set by appropriate DC level at pin AS (see
Table 5-6 Address selection on page 11).
While applying the supply voltage, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and when VCC falls below 3.2 V. It will be reset at the end of a READ operation.
Wireless Components
3 - 10
Specification, March 2000
4
Applications
Contents of this Chapter 4.1 Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Wireless Components
4-1
Specification, March 2000
TUA6020
preliminary
Applications
4.1 Circuit
47n 2k7
560 22n BB659 2k7 IFOUT RLoad = 75 4n7 BA892 82p 1p 1k 3k3 120p VCC 100n 1k 100k 220 33k 560 + 33 V 100n
1k8
1k8
BB565 15p
L1
L2
L3
2:10**)
12p 12k
C2 2n2
4n7 1p2 28 27 1p2 26 1p2 25 1p2 24 2p7 23 2p2 22 2p2 21 2p7 20 19 18 17 16 15
C1 100n
TUA6020
1 2p2 2 3 4 5 6 7 8 9 10 11 12 13 14
22p
22p
1n
18p L4 68p 4n7 68p 47n 220 220 4 MHz 100p 100p 4n7 4n7 4n7 4n7
1:1*)
LOW/ MID HIGH RGen = 75 VCC RGen = 75
SDA
SCL
AS
PHIGH PLOW
PMID
Application Circuit
Figure 4-1
Evaluation Board Table 4-1 Coils turns L1 L2 L3 L4 *) **) 1.5 2.5 8.5 14.5 2.4 mm 3 mm 3 mm 4 mm wire 0.5 mm 0.5 mm 0.5 mm 0.3 mm
Table 4-1 Recommended band limits in MHz RF input min LOW MID HIGH 48.25 147.25 432.25 max 140.25 423.25 855.25 Oscillator min 87.15 193.15 471.25 max 186.15 462.25 894.25
TOKO B4F Type 617DB-1023 TOKO 7KL600 GCS-A1010DX
Wireless Components
4-2
Specification, March 2000
5
Reference
Contents of this Chapter 5.1 5.1.1 5.1.2 5.1.3 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-5 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Table 5-6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-7 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-8 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-9 IC frequency range selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.5 5.5.1 5.5.2 5.5.3 5.5.4 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Gain (GV) test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . . . . 5-13 Gain (GV) test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Matching circuit for optimum noise figure in LOW/MID band . . . . . . 5-14 Noise Figure Test Set-up in LOW/MID band . . . . . . . . . . . . . . . . . . 5-14 Noise Figure Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . . . . . 5-15 Cross modulation Test Set-up in LOW/MID band. . . . . . . . . . . . . . . 5-15 Cross modulation Test Set-up in HIGH band . . . . . . . . . . . . . . . . . . 5-16 Measurement of fref and fdiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Electrical Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Input admittance (S11) of the LOW/MID band mixer input . . . . . . . . 5-17 Input impedance (S11) of the HIGH band mixer input . . . . . . . . . . . 5-17 Output admittance (S22) of the Mixer output . . . . . . . . . . . . . . . . . . 5-18 Output impedance (S22) of the IF output . . . . . . . . . . . . . . . . . . . . . 5-18
Wireless Components
5-1
Specification, March 2000
TUA6020
preliminary
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature T AMB=--20C ... + 85C Parameter 1). Symbol Limit Values min Supply voltage Junction temperature Storage temperature Thermal resistance (junction to ambient) PLL CP VCP ICP Crystal oscillator pin XTAL VXTAL IXTAL Bus input/output SDA Bus output current SDA Bus input SCL Chip address switch AS Tuning voltage output (loop filter) Port outputs PLOW, PMID, PHIGH VSDA ISDA(L) VSCL VAS VT VP IP(L) Total port output current Mixer-Oscillator Mixer inputs LOW/MID Mixer inputs HIGH Vi Vi Ii -5 -0.3 3 2 6 V V mA IP(L) -0.3 -0.3 -0.3 -0.3 -1 -5 -0.3 VCC 5 VCC VCC 35 VCC 25 40 -0.3 3 1 VCC V mA V mA V mA V V V V mA mA tmax = 0.1 sec. at 5.5 V tmax = 0.1 sec. at 5.5 V open collector VCC TJ TStg RthJA -40 -0.3 max 6 +150 +125 120 V C C K/W Unit Remarks
Wireless Components
5-2
Specification, March 2000
TUA6020
preliminary
Reference
Table 5-1 Absolute Maximum Ratings, Ambient temperature T AMB=--20C ... + 85C (continued) Parameter 1) Symbol Limit Values min Oscillator base voltage Oscillator collector voltage ESD-Protection 2). all pins VESD 1 kV VB VC -0.3 max 3 VCC V V Unit Remarks
1). All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flow into the pin and currents with a negative sign flow out of pin. 2). According to MIL STD 883D, method 3015.7 and EOS/ESD assn. standardS5.1 - 1993
Wireless Components
5-3
Specification, March 2000
TUA6020
preliminary
Reference
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Range Parameter Symbol Limit Values min Supply voltage Programmable divider factor LOW/MID Mixer input frequency range HIGH Mixer input frequency range LOW/MID Oscillator frequency range HIGH Oscillator frequency range Ambient temperature VCC N fMIXV fMIXU fOH fOU Tamb +4.5 256 30 400 65 430 -20 max +5.5 32767 500 900 560 950 +85 MHz MHz MHz MHz C V Unit Test Conditions L Item
Wireless Components
5-4
Specification, March 2000
TUA6020
preliminary
Reference
5.1.3
AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Table 5-3 AC/DC Characteristics with TA 25 C, VCC Symbol min Supply Supply voltage Current consumption VCC ICC 4.5 56 5 70 5.5 84 V mA Limit Values typ max Unit Test Conditions L Item
Digital Unit
PLL Crystal oscillator connections XTAL Crystal frequency Crystal resistance Oscillation frequency Input impedance fXTAL RXTAL fXTAL ZXTAL 3.2 10 3,99975 -500 4,000 -700 4.0 4.8 100 4,00025 -900 MHz MHz series resonance series resonance fXTAL = 4 MHz fXTAL = 4 MHz
Charge pump output CP HIGH output current LOW output current Tristate current Output voltage ICPH ICPL ICPZ VCP 1.0 90 22 220 50 +1 2.5 300 75 A A nA V CP = 1, V CP = 2 V CP = 0, V CP = 2 V T0 = 1, VCP = 2 V PLL locked
Drive output VT (open collector) HIGH output current LOW output voltage I2C-Bus Bus inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current VIH VIL IIH IIL -10 3 0 5.5 1.5 10 V V A A VIH = V S VIL = 0 V ITH VTL 10 0.4 A V VTH = 33 V, T0 = 1 ITL = 1.0 mA
Bus output SDA (open collector) HIGH output current LOW output voltage IOH VOL 10 0.4 A V VOH = 5.5 V IOL = 3 mA
Wireless Components
5-5
Specification, March 2000
TUA6020
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VCC (continued) Symbol min Edge speed SCL,SDA Rise time Fall time Clock timing SCL Frequency HIGH pulse width LOW pulse width Start condition Set-up time Hold time Stop condition Set up time Bus free Data transfer Set-up time Hold time Input hysteresis SCL, SDA Pulse width of spikes which are suppressed Capacitive load for each bus line tsudat thdat Vhys tsp CL 0 0.1 0 200 50 400 s s mV ns pF tsusto tbuf 0.6 1.3 s s tsusta thsta 0.6 0.6 s s fSCL tH tL 0 0.6 1.3 400 kHz s s tr tf 300 300 ns ns Limit Values typ max Unit Test Conditions L Item
Port outputs PLOW, PMID, PHIGH (open collector) HIGH output current LOW output voltage IPOH VPOL 1 0.5 A V VPOH = 5 V IPOL = 25 mA
Address selection input AS HIGH input current LOW input current IASH IASL -50 50 A A VASH = 5 V VASL = 0 V
Wireless Components
5-6
Specification, March 2000
TUA6020
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VCC (continued) Symbol min Limit Values typ max Unit Test Conditions L Item
Analog Unit
LOW/MID Band Section (including IF amplifier) Voltage gain GV 20 23 26 dB fRF = 43.25 to 463.25 MHz, fIF = 33.4 to 58.75 MHz fRF = 43.25 to 463.25 MHz fRFw = 48.25 MHz fRFw = 399.25 MHz
Mixer noise figure Output voltage causing 0.8% of crossmodulation in channel, see 5.4.6 on page 15 Input IP2
NF Vi Vi
9 118 117
11
dB dBV dBV
IIP2
137
dBV
fRF1 = 48.25 MHz fRF2 = 98.50 MHz, PRF1 = PRF2 fRF1 = 415.25 MHz fRF2 = 832.50 MHz, PRF1 = PRF2 fRF1 = 48.25 MHz fRF2 = 49.25 MHz PRF1 = PRF2 fRF1 = 252.25 MHz fRF2 = 253.25 MHz, PRF1 = PRF2 parallel equivalent circuit, fRF = 100 MHz parallel equivalent circuit, fRF = 100 MHz VS = 5 V 10% T = 25=C t = 5 s up to 15 min after switching on f = 10 kHz fRF = 48.25 MHz f = 10 kHz fRF = 399.25 MHz
IIP2
137
dBV
Input IP3
IIP3
119
dBV
IIP3
119
dBV
Mixer input impedance
Ri Ci
0.5
1 2
1.5 3 400 500 100
k pF kHz kHz kHz dBV dBV
Oscillator frequency shift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator pulling, PLL unlocked
fOsc(V) fOsc(T) fOsc(t) Vi 100 100 108 108
Vi
Wireless Components
5-7
Specification, March 2000
TUA6020
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VCC (continued) Symbol min N + 5 pulling, PLL unlocked N+5 -50 Limit Values typ max dBc fRF = 48.25 MHz, fRF1 = 83.25 MHz, PRF=P RF1 = 80dBV fRF = 399.25 MHz, fRF1 = 439.25 MHz, PRF=P RF1 = 80dBV fm = 1kHz fm = 10kHz Vi = 80 dBV Unit Test Conditions L Item
N+5
-50
dBc
Oscillator phase noise 1). IF suppression
OSC OSC a
-58 -88 15
-60 -90 20
dBc/Hz dBc/Hz dB
HIGH Band Section (including IF amplifier) Voltage gain GV 31 34 37 dB fRF = 367.25 MHz to 863.25 MHz, fIF = 33.4MHz to 58.75 MHz fRF = 367.25 to 615.25 MHz fRF = 623.25 to 863.25 MHz fRFw = 503.25 MHz fRFw = 799.25 MHz fRF1 = 423.25 MHz fRF2 = 848.50 MHz, PRF1 = PRF2 fRF1 = 503.25 MHz fRF2 = 504.25 MHz PRF1 = PRF2 fRF1 = 799.25 MHz fRF2 = 800.25 MHz PRF1 = PRF2 serial equivalent circuit, fMixU = 600 MHz serial equivalent circuit, fMixU = 600 MHz VS = 5 V 10% T = 25=C t = 5 s up to 15 min after switching on
Mixer noise figure
NF
6 7
9 10
dB dB dBV dBV
Output voltage causing 0.8% of crossmodulation in channel, see 5.4.7 on page 16 Input IP2
Vi Vi IIP2
116 117
139
dBV
Input IP3
IIP3
108
dBV
IIP3
108
dBV
Mixer input impedance
Ri Li
14 6
20 10
26 14 400 800 100
nH kHz kHz kHz
Oscillator frequency shift, PLL unlocked Oscillator frequency drift, PLL unlocked Oscillator frequency drift, PLL unlocked
fOsc(V) fOsc(T) fOsc(t)
Wireless Components
5-8
Specification, March 2000
TUA6020
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VCC (continued) Symbol min Oscillator pulling, PLL unlocked Vi 100 100 -50 Limit Values typ 108 108 max dBV dBV dBc f = 10 kHz fRF = 375.25 MHz f = 10 kHz fRF = 847.25 MHz fRF = 471.25 MHz, fRF1 = 511.25 MHz, PRF =PRF1 = 80dBV fRF = 847.25 MHz, fRF1 = 887.25 MHz, PRF=P RF1 = 80 dBV fm = 1kHz fm = 10kHz Vi = 80 dBV Unit Test Conditions L Item
Vi N + 5 pulling, PLL unlocked Vi
Vi
-50
dBc
Oscillator phase noise
1)
OSC OSC a
-58 -88 15
-60 -90 20
dBc/Hz dBc/Hz dB
IF suppression SAW preamplifier IF output impedance
RIF LIF
125 10
nH
serial equivalent circuit, fIF = 38.9 MHz
Rejection at the IF outputs Divider interference level
2).
Vo INT S02 66
30
dBV dBc fRF = 76.25 MHz PRF = 80 dBV
Channel S02 beat rejection 3).
This value is only guaranteed in lab. 1). Measured in the evaluation board (see Chapter 4), worst case in band 2). This is the level of divider interferences close to the IF frequency. For example channel S3: fOSC = 158.15 MHz, 1/4 fOSC = 39.5375 MHz. Measured in the evaluation board (see Chapter 4). 3). Channel S02 beat is the interfering product of fRF, fIF and fOSC of channel S02, fbeat = 37.35 MHz. The possible mechanisms are fOSC - 2 x fIF or 2 x fRFpix - fOSC. Measured in evaluation board (see Chapter 4).
Wireless Components
5-9
Specification, March 2000
TUA6020
preliminary
Reference
5.2 Programming
Table 5-4 Bit Allocation Read / Write Byte Write Data Address Byte Progr. Divider Byte 1 Progr. Divider Byte 2 Control Byte Bandswitch Byte Read Data Address Byte Status Byte 1 POR 1 FL 0 x 0 x 0 x MA1 x MA0 x 1 x A A 1 0 N7 1 x 1 N14 N6 CP x 0 N13 N5 T1 x 0 N12 N4 T0 x 0 N11 N3 FP x MA1 N10 N2 RSA PHIGH
1).
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
MA0 N9 N1 RSB PLOW
1). 2).
0 N8 N0 OS PMID
1). 2).
A A A A A
1). see Table 5-9 IC frequency range selection on page 11 2). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.
Table 5-5 Description of symbols Symbol MA0, MA1 N14 to N0 CP T1, T0 FP RSA, RSB OS Description Address selection bits (see Table 5-6 Address selection on page 11) programmable divider bits: N = 214 x N14 + 213 x N13 + ..... + 23 x N3 + 22 x N2 + 21 x N1 + N0 charge pump current:bit = 0: charge pump current = 50 A bit = 1: charge pump current = 220 A test bits (see Table 5-7 Test modes on page 11) reserved for future purposes, actually ignored, default: 1 reference divider bits (see Table 5-8 Reference divider ratio on page 11) tuning amplifier control bit:bit = 0: enable VT bit = 1: disable VT NPN ports control bits:bit = 0: NPN open-collector output is inactive bit = 1: NPN open-collector output is active (see Table 5-9 IC frequency range selection on page 11) PLL lock flagbit = 1: loop is locked Power-on reset flag flag is set at power-on and reset at the end of READ operation don`t care
PLOW, PMID, PHIGH
FL POR x
Wireless Components
5 - 10
Specification, March 2000
TUA6020
preliminary
Reference
Table 5-6 Address selection Voltage at AS (0...0.1) * V CC open circuit (0.4...0.6) * V CC (0.9...1) * V CC MA1 0 0 1 1 MA0 0 1 0 1
Table 5-7 Test modes Test mode Normal operation Charge pump output, CP is in high-impedance state PLOW = fdiv output, PMID = fref output not used T1 0 0 1 1 T0 0 1 0 1
Table 5-8 Reference divider ratio Reference divider ratio 80 128 24 64 1). With a 4 MHz quartz. fref 1). 50 kHz 31.25 kHz 166.7 kHz 62.5 kHz RSA 0 0 1 1 RSB 0 1 0 1
Table 5-9
IC frequency range selection Bit 2 (PHIGH) 0 0 1 Bit 1 (PLOW) 1). 1 0 0 Bit 0 (PMID) 1.) 0 1 0
Frequency range LOW/MID (VHF) LOW/MID (VHF) HIGH (UHF)
1). In a tuner PLOW and PMID are interchangeable. Both bits switch the IC into LOW/MID (VHF) mode.
Wireless Components
5 - 11
Specification, March 2000
Wireless Components
5.3 I2C Bus Timing Diagram
Addressing
Ack.
1st Byte
Ack.
2nd Byte Ack.
3rd Byte Ack. 4th Byte
Ack.
MA MA R/W
Note: SDA:
SCL:
5 - 12 Specification, March 2000
Telegram examples:
Abbreviations:
Start-ADB-DB1-DB2-CB-BB-Stop Start-ADB-CB-BB-DB1-DB2-Stop Start-ADB-CB-AB-DB1-DB2-Stop Start-ADB-DB1-DB2-Stop Start-ADB-CB-BB-Stop
Start= start condition ADB= address byte DB1= prog. divider byte 1 DB2= prog. divider byte 2 CB= Control byte BB= Bandswitch byte Stop= stop condition
TUA6020
Reference
preliminary
TUA6020
preliminary
Reference
5.4 Test Circuits
5.4.1
Gain (GV) test Set-up in LOW/MID band
50 Vmeas RMS Votmeter
LOW/ MIDIN
IFOUT
Transformer N1 V0 C V'meas N2 50 spectrum analyser
V
50
Vi
Device under Test
IFOUT
N1 : N2 = 10 : 2 turns
GVHF2
Zi >> 50 => V i = 2 x Vmeas = 80 dBV Vi = Vmeas + 6dB = 80 dBV V0 = V'meas + 16 dB (transformer ratio N1:N2 and transformer loss) Gv = 20 log(V0 / Vi)
5.4.2
50 Vmeas RMS Votmeter
V
Wireless Components

Gain (GV) test Set-up in HIGH band
HIGHIN IFOUT
Transformer N1 V0 C V'meas N2 50 spectrum analyser
50
Vi
Balun 1:1
Device under Test
HIGHIN IFOUT
N1 : N2 = 10 : 2 turns
GUHF2
Vi = Vmeas = 70 dBV V0 = V'meas + 16 dB (transformer ratio N1:N2 and transformer loss) Gv = 20 log(V0 / Vi) + 1 dB (1 dB = insertion loss of balun)
5 - 13
Specification, March 2000
TUA6020
preliminary
Reference
5.4.3
Matching circuit for optimum noise figure in LOW/MID band
22p In
1n Out 7 turns wire 0.5 mm coil 5.5 mm In
15p
1n Out
22p
50 semi rigid cable 300 mm long 96 pF/m 33dB/100m
22p
Nfm
For fRF = 50 MHz loss = 0 dB image suppression = 16 dB
For fRF = 150 MHz loss = 1.3 dB image suppression = 13 dB
5.4.4
Noise Figure Test Set-up in LOW/MID band
Noise Source
IN
OUT
LOW/ MIDIN
IFOUT
Matching Circuit
Device under Test
IFOUT
N1 : N2 = 10 : 2 turns NF = NFmeas - loss of matching circuit (dB)
Wireless Components
5 - 14

Transformer N1 C N2
Noise Figure Meter
NFVHF2
Specification, March 2000
TUA6020
preliminary
Reference
5.4.5
Noise Figure Test Set-up in HIGH band
Noise Source
HIGHIN IFOUT
Transformer N1 C N2
Balun 1:1
Device under Test
HIGHIN IFOUT
Noise Figure Meter
N1 : N2 = 10 : 2 turns loss of balun = 1 dB NF = NFmeas - loss of balun (dB)
NFUHF2
5.4.6
Cross modulation Test Set-up in LOW/MID band
Vmeas unwanted signal source AM = 80 % A 50 C RMS Votmeter
V
50
LOW/ MIDIN
IFOUT
Transformer N1 V0 C N2
18 dB attenuator 38.9 MHz
Hybrid
50 B wanted signal source D 50
Vi
Device under Test
IFOUT
V
V'meas RMS Votmeter
50 modulation analyser
N1 : N2 = 10 : 2 turns
XVHF2
Zi >> 50 => Vi = 2 x Vmeas V'meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss) wanted output signal at fpix, Vo = 100 dBV unwanted output signal at fsnd, 80 % AM modulated with 1 kHz
Wireless Components

5 - 15
Specification, March 2000
TUA6020
preliminary
Reference
5.4.7
Cross modulation Test Set-up in HIGH band
Vmeas unwanted signal source AM = 80 % A 50 C RMS Votmeter
V
50
HIGHIN IFOUT
Transformer N1 V0 C N2
18 dB attenuator 38.9 MHz
Hybrid
50 B wanted signal source D 50
Vi
Balun 1:1
Device under Test
HIGHIN IFOUT
V
V'meas RMS Votmeter
50 modulation analyser
N1 : N2 = 10 : 2 turns
XUHF2
V'meas = V0 - 16 dB (transformer ratio N1:N2 and transformer loss) wanted output signal at fpix, Vo = 100 dBV unwanted output signal at fsnd, 80 % AM modulated with 1 kHz
5.4.8
Device under Test
18p 4 MHz
Wireless Components

Measurement of fref and fdiv
VVCC
+5V
Test Mode: T1 = 1, T0 = 0 5k 5k
PMID
fref
Counter
fQ = fref * R R: reference divider ratio
PLOW fdiv
Counter
fVCO = fdiv * N N: divider ratio
MEAS_COF
5 - 16
Specification, March 2000
TUA6020
preliminary
Reference
5.5 Electrical Diagrams
5.5.1
Input admittance (S11) of the LOW/MID band mixer input
Y0 = 20mS (single ended)
1
0.9
0.8
1.5
0.7
0.6
0.5
0.4
2 3
1.5 1 0.9 0.8 0.7 0.6 0.5 0.4
0.3
0.3
0.2
0.1
20
10
5
4
3
2
20
48.25 MHz
0.1
10
407.25 MHz
0.2 5
4
3
0.4
1.5
5.5.2
Input impedance (S11) of the HIGH band mixer input
Z0 = 50 (balanced)
0.7
0.8
0.9
1
1
0.9
0.8
0.6
1.5
0.7
0.6
0.5
2
0.5
2
3
0.3
4
5
855.25 MHz
10 0.1
415.25 MHz
20
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 0.9 1
1.5
Rdiff
10
0
20
20
2
3
4
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Wireless Components
5 - 17
1
1.5
2
Specification, March 2000
5
0.2
10
0.1
5
0
4
0.3
3
0.4
4
0.2 0.2 5
10
20
0.1
TUA6020
preliminary
Reference
5.5.3
Output admittance (S22) of the Mixer output
Y0 = 20mS (balanced)
1
0.9
0.8
1.5
0.7
0.6
0.5
0.4
2 3
1.5 1 0.9 0.8 0.7 0.6 0.5 0.4
0.3
0.3
0.2
20
4
3
0.4
1.5
5.5.4
Output impedance (S22) of the IF output
Z0 = 50 (single/ double ended)
0.7
0.8
0.9
1
1
0.9
0.8
0.6
1.5
0.7
0.6
0.5
2
0.5
2
3
0.3
4
5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 0.9 1
1.5
10
0
Rse
0.1
Rdiff
20
20
10
2
3
4
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Wireless Components
5 - 18
1
1.5
2
Specification, March 2000
5
0.2
5
0.2
5
0.1
10
10
20
0
Rdiff 38.9 MHz
4
0.3
0.1
20
10
5
4
3
2
3
0.4
4
0.2 0.2 5
0.1 10
20
0.1

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